Delay circuits are used to shift signals and/or set oscillator frequencies. A common oscillator circuit is created through a series of stages in which the output of one stage is input to the next state and the output of the last stage of the oscillator is fed back to the first stage of the oscillator. Each stage of an oscillator represents a propagation delay. For example, three inverters connected in series in which the output of the last inverter is input to the first inverter creates an oscillator in which an oscillator clock frequency has a period equal to twice the sum of the propagation delays of each inverter.
The current state of timing delay technology is faced with four major issues. First, it is desirable to accurately and relatively easily program and set the delay to the desired value with the actual circuits. As the clock speed gets faster and the die becomes denser, the available timing budget is quickly reduced. That increases the need for a robust and accurate way to shift a signal. Second, as the clock rate increases in digital integrated circuits, it becomes more challenging to accurately maintain the clock signal at a desired frequency over PVT (process, voltage, and temperature) variations. Process, voltage, and temperature behavior varies from device to device, with given tolerances. Unfortunately, these variations also change the value of the delay. It is absolutely necessary to have the ability to calibrate and adjust the delay whenever there is a need. Third, it is desirable to program and set the delay and calibrate the delay while using minimal power and die area. It is important to design with as few cells (i.e., thus, permitting a smaller die area) and as low power consumption as possible to have a competitive advantage. Fourth, flexibility of the techniques if advantageous. As the complexity of circuit designs grow, so does the need to support various timing and speed requirements. It would be advantageous to have a scheme to support the different requirements for different applications.
There are many ways to shift a signal, each way having its advantages and disadvantages. So far, analog phase locked loops (PLLs), delayed-locked loops (DLLs), fixed delay cells, and some forms of digital delay scheme have been used to address these issues. Unfortunately, none of the current solutions have been able to solve all of the above problems. Although PLLs and DLLs are proven techniques to retime the clock or delay the clock 90, 180, or 270 degrees and to calibrate and adjust the delay and/or frequency over PVT, they consume a relatively large amount of power, usually require large die area, are very sensitive to switching noise, and are usually limited to shifts of 90, 180, 270 and 360 degrees only. Fixed delay cells, an alternative to PLLs and DLLs, are small and easy to use, but they are not PVT calibrated and they are limited to one frequency only. These and other currently available digital delay schemes are performed for some specific applications, but they lack the flexibility and require too much die area for the current and forthcoming technology.
Therefore, it would be desirable to provide a timing delay scheme that is easy to calibrate and is able to adjust the delay in small time increments for applications such as oscillator circuits.